Computer systems often operate together. To do so, they are connected through an interface. This interface may have a synchronizer to ensure that the signals generated by one system are synchronized in the time domain with signals of a second system so that communications between the two systems is effected.
When conventional synchronization methods have been used, the synchronized signals, in many cases, could not be input to the destination system because the proper set-up and hold time limitations could not be met since such destination systems had critical timing limitations for such synchronized signals. This becomes even more complicated if the synchronous signals have multiple asynchronous sources. More specifically, each of the multiple asynchronous sources that were used to generate the synchronous signal has its own synchronizer and the output of these synchronizers are input to an OR gate. The OR gate function delayed the synchronous signal even more and made meeting the set-up and hold time requirements even more difficult.
A synchronizing circuit of the type just described is shown in FIG. 1 generally at 100. The multiple asynchronous sources for generating synchronous signal 124 are ASYNC SOURCE A signal 102, ASYNC SOURCE B signal 110, and ASYNC SOURCE C signal 116. The synchronization of each of these asynchronous source signals is carried out by a two step synchronizer consisting of two D-type flip-flops. ASYNC SOURCE A signal 102 is synchronized by series connected flip-flops 104 and 108, ASYNC SOURCE B signal 110 by series connected flip-flops 112 and 114, and ASYNC SOURCE C signal 116 by series connected flip-flops 118 and 120. All of these flip-flops are clocked by the destination system clock signal 106.
The outputs of last stage flip-flops 108, 114, and 120 are input to OR gate 122. Each of these output signals has been synchronized in the time domain of the destination system. The output of OR gate 122 is synchronous signal 124 which is synchronized in the time domain of the destination system except for the delays associated with carrying out the OR function.
To minimize the delays caused by the OR function, ideally, the last stage flip-flops 108, 114, and 120 of the respective synchronizers are placed as physically close to the destination system as possible. This assists in reducing the capacitance between the systems and, thus, the time necessary to assert and de-assert the synchronized signal. However, this method of reducing delays becomes difficult when each of the multiple sources has its own synchronizer because only the OR gate, such as OR gate 122, can be placed next to the destination system because of physical constraints of any system implementing a circuit such as that shown in FIG. 1. Moreover, the greater the number of multiple sources, the greater the distance the last stages of the separate synchronizers will be from the destination system. The lengthening of the distance that the last stage flip-flops are from the destination system also adds to the timing of synchronous signal 124 and makes meeting the set-up and hold time requirements even more difficult.
This same problem exists in a bit-sliced integrated circuit. For example, a particular pin of the circuit may assume several functions depending on its assigned "personality", and each of these functions may require an on-chip synchronizer. The timing problem described above will then occur with respect to the timing delays associated with the OR function and the last stages of the synchronizers of the number of multiple sources being able to be in close proximity to an output driving pin.
The present invention overcomes these and other problems as set forth in the remainder of the specification and referring to the attached drawings.